VITAL Model of a Pullup Device Without Delay Back Annotation
A pullup device without delay back annotation (FIG. 1) is simply a resistive connection to the bias supply VDD, and is trivially modeled as a connection to a weak `1`, i.e. state `H` in the 9-state logic system defined in the IEEE package STD.sub.-- LOGIC.sub.-- 1164 (FIG. 2).
Conceptually, the pullup device of FIG. 1 can be thought of as supplying or outputting a weak `1`at node O. Hence, the mode of port O in FIG. 2 is `out`.
According to the 1995 version of the IEEE VITAL standard ASIC Modeling Specification 1076.4, (which is incorporated herein by reference) a VITAL Level 1 architecture must contain at least one VITAL process statement or VITAL concurrent procedure call. Since the architecture in FIG. 2 contains neither of these two constructs, it can only be decorated with a VITAL.sub.-- LEVEL0 attribute, which designates a VITAL Level 0 architecture.
Note that the reference to the VITAL.sub.-- Timing package in the second library use statement is required, even though the model does not have delay back annotation. This is because the package contains definitions for the VITAL.sub.-- LEVEL0 and VITAL.sub.-- LEVEL1 attributes.
Rationale for Developing a Pullup Model with Delay Back Annotation
The modeling problem becomes significantly more complex if the model is required to import a delay via a timing generic and apply it to model the transition delay from the high impedance state `Z` to the weak `1` state `H` at port O. In practice, this modeling requirement can arise in a high speed design employing wired logic. Consider, for example, two tristate buffers TBUF1 and TBUF2 whose output ports O1 and O2 are tied together and connected to the port O of a pullup device PULLUP (FIG. 3).
In FIG. 3, the numbers are delay values in nanoseconds. Two numbers separated by a colon specify rise and fall delay values, respectively. For example, in TBUF1, 2.5:2.5 denotes a rise delay of 2.5 ns from port I1 to port O, and a fall delay of 2.5 ns from port I1 to port O.
In FIG. 3, tristate enable ports T1 and T2 are assumed to be active high. (Active high means that the buffer output will be high impedance when the tristate control signal is high.) Referring again to TBUF1, port O will go to the high impedance state `Z` 3.9 ns after port T1 goes to `1`. Port O will go to `0` or `1` 5.2 ns after port T1 goes to `0`. The delay of 9.5 ns shown for PULLUP signifies that port O will go to the `H` state 9.5 ns after it enters the `Z` state, but only if the model for PULLUP allows back annotation of a delay for use in modeling the `Z`-to-`H` transition. The simple model of FIG. 2 doesn't allow this back annotation. Therefore, the delay of 9.5 ns has to be accounted for by adding it to the tristate enable delay of 3.9 ns as shown in FIG. 4.
In FIG. 4, assuming TBUF1 is on (i.e. port T1 is `0`), port I1 is `0`, TBUF2 is off (i.e., port T2 is `1`) and port I2 is `1`, a `0` to `1` transition at port T1 will cause port O to go from `0` to `H` 13.4 ns later, without first going to `Z`. Therefore, for contention free operation, TBUF2 cannot be switched on until (13.4 ns-5.2 ns) i.e. 8.2 ns after TBUF1 has been switched off. For high speed applications, where every nanosecond counts, this long delay of 8.2 ns may not be acceptable. Hence the rationale for developing a pullup model with delay back annotation.